Integrated chips are made by a process that includes a design step and a subsequent fabrication step. During the design step, a layout of an integrated chip (IC) is generated as an electronic file. The layout includes geometric shapes corresponding to structures to be fabricated on-chip. During the fabrication step, the layout is formed onto a semiconductor workpiece.
The resolution that a conventional lithography tool can achieve is limited to 45 nanometer (nm) half pitch. To continue to use existing lithography tools to resolve smaller spaces, double patterning methods have been developed. Double patterning method involves splitting (e.g., dividing or separating) a target circuit pattern into two separate patterns. The two separate patterns are then formed separately on a single layer of a substrate using two separate masks in succession. By breaking a layout into multiple different masks, a minimum line spacing in the combined pattern is reduced while maintaining good resolution.
To use double patterning methods, a target circuit pattern must be double-patterning compliant, which means the target circuit pattern is capable of being decomposed into two separate patterns that each may be formed in a single layer of photoresist using the conventional lithography tool. For ease of visualization, patterns assigned to the same or different masks for exposing the same layer are often drawn in different colors. It has been observed that this color-assigning procedure can be problematic. For example, during the decomposition process of a circuit pattern, a first mask for forming a first decomposed pattern may be randomly represented as a first color (e.g., black color) in an electronic design automation (EDA) layout tool, and a second mask for forming a second decomposed pattern may be represented as a second, different color (e.g., gray color) in the circuit design tool. However, in the next decomposition process of the same circuit pattern, a first mask for forming the first decomposed pattern may be randomly represented as a second color (e.g., gray color) in the circuit design tool while a second mask for forming the second decomposed pattern may be represented as a first color (e.g., black color) in the EDA layout tool. In other words, the EDA layout tool may generate different coloring results (i.e., different photomask assignments) from time to time even though the same circuit pattern is analyzed.
Coloring results may differ from chip to chip due to design change or different database hierarchy adapted by different clients/chip designers. Coloring results may also differ from location to location within the same chip for the same reasons. Inconsistencies in coloring results can cause uncertainties in the manufacture of semiconductor devices.